At the 2026 North America Technology Symposium held yesterday, TSMC unveiled its general-purpose process technology roadmap extending through 2029. The core highlights of this announcement include the 1.2nm and 1.3nm class manufacturing processes, named A12 and A13 respectively; a surprising extension of the N2 family dubbed N2U; and a confirmed plan to not utilize High-NA EUV lithography at any process node through 2029. Perhaps the most significant takeaway from this technical briefing is TSMC's formal establishment of a diversified development strategy tailored for next-generation process nodes.
Kevin Zhang, Senior Vice President of Business Development and Global Sales and Assistant to the COO at TSMC, stated:
"Last year, we announced the A14 process, which utilizes second-generation nanosheet transistor technology and is scheduled for mass production in 2028."
"This year, we are introducing derivatives of the A14, including A13 and A12, both planned for mass production in 2029. A13 is an incremental enhancement of A14, achieved primarily through optical shrink. It reduces chip area by approximately 6% while maintaining full design rule and electrical compatibility, allowing customers to benefit with minimal redesign."
Rewriting the Rules of the Game
In the past, the vast majority of TSMC's revenue came from the smartphone industry. However, in recent years, the growth rates of AI and High-Performance Computing (HPC) have surpassed those of mobile terminals. This shift is clearly reflected in the company's planning: TSMC's latest roadmap explicitly adopts a forked strategy, differentiating advanced process nodes based on terminal market demand rather than pursuing a "one-size-fits-all" solution.
Accordingly, TSMC will adopt a new process release strategy: launching one new process annually for consumer terminals, and one new process every two years for heavy-duty AI and HPC applications.
On one hand, processes such as N2, N2P, N2U, A14, and A13 are targeted at smartphones and terminal devices. In these sectors, cost, energy efficiency, and IP reuse are paramount, making high design compatibility highly desirable. As long as TSMC can launch a new generation node annually, slight performance improvements are acceptable.
On the other hand, nodes like A16 and A12 are designed for AI and HPC applications. These must deliver significant performance leaps to justify the cost of technology switching, with cost being a secondary concern. These nodes will integrate the Super Power Rail (SPR) backside power architecture to address power integrity and current transmission limitations in AI data centers and HPC loads, delivering tangible improvements in performance, power consumption, and transistor density—despite a release cadence of one generation every two years.
A13 and N2U: New Nodes for Consumer Terminals
Last year, TSMC introduced the A14 process, which employs second-generation Gate-All-Around (GAA) nanosheet transistors. Leveraging NanoFlex Pro technology for greater design flexibility, it is expected to become TSMC's flagship process for high-end smartphones and terminal devices in 2028. This year, TSMC announced the launch of A13, based on A14.
TSMC's A13 is an optical shrink version of A14, designed to further enhance efficiency with minimal changes. A13 reduces linear dimensions by approximately 3% (to about a 97% scale), increasing transistor density by roughly 6%, while maintaining completely compatible design rules and electrical characteristics with A14. From multiple perspectives, A13 continues TSMC's long-standing tradition of optical shrinking (seen in N12, N6, N4, N3P), although such processes typically yielded more significant benefits in the past. This approach allows TSMC customers to reuse existing IP with almost no redesign, albeit with relatively limited performance gains.
While A14 will achieve node-level upgrades in power, performance, and density, chip and IP designers must adopt new tools, IP, and design methodologies to unlock its potential. In contrast, A13 achieves incremental improvements through Design Technology Co-Optimization (DTCO), yielding benefits without requiring any design changes. A13 is expected to enter production in 2029.
In addition to launching the new A14 node in 2028, TSMC plans to provide customers with a low-cost upgrade path for N2 architecture designs via N2U. N2U is the third-year extension of the N2 platform, achieved through DTCO: it offers a 3%–4% performance improvement at the same power, an 8%–10% power reduction at the same frequency, and a slight logic density increase of 2%–3%. This node will remain compatible with N2P IP, enabling customers (especially in consumer electronics) to develop new products without switching to a completely new process, thereby avoiding huge cost investments. For instance, if a company plans to develop mid-range products in 2027 based on high-end chip IP from N2P, they can directly utilize N2U in 2028 to achieve this.
Zhang Xiaqiang stated: "We will continue to expand the 2nm platform through N2U, leveraging Design Technology Co-Optimization to further enhance performance, power, and density. Our strategy is to continuously iterate and optimize after each node launch, maximizing customers' return on design investment while delivering incremental PPA (Performance, Power, Area) benefits."
A16, A12, and N2X: Pursuing Ultimate Performance Regardless of Cost
Although TSMC's N2 will serve both consumer terminals and data center applications, the company is also developing the A16 process, equipped with a Super Power Rail backside power architecture, specifically customized for high-performance data center scenarios. Simply put, A16 is N2P with SPR. Based on first-generation GAA nanosheet transistors, it offers significant advantages in power, performance, and density compared to N2 and N2P, albeit at a higher cost.
Notably, TSMC currently lists A16 as a mass production process for 2027, a delay from the previous timeline of 2026.
Zhang Xiaqiang explained: "A16 will be ready in 2026, but actual product volume depends on customer adoption; we expect large-scale mass production in 2027. This is why we have aligned its timeline to 2027."
Interestingly, the launch of A16 will not replace N2X—the latter is a performance-enhanced version of N2P using traditional front-side power delivery, pushing the design frequency of the N2 series to its limits.
Following A16 will be A12, scheduled for release in 2029. It is expected to bring a full node-level generational advantage to TSMC's data center nodes. Although TSMC has not disclosed specific data, the improvement magnitude of A12 relative to A16 can be benchmarked against A14 relative to N2, as it will utilize second-generation GAA nanosheet transistors and NanoFlex Pro technology.
Zhang noted: "A16 is our first-generation technology featuring Super Power Rails (backside power). A12 represents the next generation... it will simultaneously shrink both front-side and back-side structures to achieve overall density gains."
High-NA EUV Will Not Appear in the Short Term
A noteworthy commonality between the A13 and A12 processes planned for launch by TSMC in 2029 is that neither requires High-NA EUV lithography equipment. This stands in stark contrast to Intel, whose 14A and subsequent nodes plan to begin using High-NA EUV lithography machines between 2027–2028.
Zhang Xiaqiang remarked: "I must say, I am amazed by our R&D team. They continue to find ways to achieve process shrinking without relying on High-NA EUV. Perhaps one day we will have to use it, but for now, we can still extract benefits from existing EUV without switching to High-NA EUV—especially given its exorbitant cost."
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